/* File pwr_ssaboxclasses.h.
*
* Generated by co_convert V6.1.4 18-MAR-2025 18:50:57.22.
* Do not edit this file.
*
* Contains type and struct declarations for the types and classes
* in volume SsabOx.
*/
#ifndef pwr_ssaboxclasses_h
#define pwr_ssaboxclasses_h
#ifndef pwr_class_h
#include "pwr_class.h"
#endif
#ifndef pwr_systemclasses_h
#include "pwr_systemclasses.h"
#endif
#include "pwr_basecomponentclasses.h"
#include "pwr_profibusclasses.h"
SsabCoDivCountEnum
typedef pwr_tEnum pwr_tSsabCoDivCountEnum;
typedef enum {
pwr_eSsabCoDivCount_No = 0,
pwr_eSsabCoDivCount_16 = 16,
} pwr_eSsabCoDivCount;
SsabCoMulCountEnum
typedef pwr_tEnum pwr_tSsabCoMulCountEnum;
typedef enum {
pwr_eSsabCoMulCount_2 = 2,
pwr_eSsabCoMulCount_4 = 4,
} pwr_eSsabCoMulCount;
SsabCoNoOfBitsEnum
typedef pwr_tEnum pwr_tSsabCoNoOfBitsEnum;
typedef enum {
pwr_eSsabCoNoOfBits_16 = 16,
pwr_eSsabCoNoOfBits_24 = 24,
} pwr_eSsabCoNoOfBits;
SsabStallActionEnum
typedef pwr_tEnum pwr_tSsabStallActionEnum;
typedef enum {
pwr_eSsabStallAction_No = 0,
pwr_eSsabStallAction_ResetInputs = 1,
pwr_eSsabStallAction_EmergencyBreak = 2,
} pwr_eSsabStallAction;
SsabDbServerConnection
typedef pwr_tEnum pwr_tSsabDbServerConnection;
typedef enum {
pwr_eSsabDbServerConnection_Down = 0,
pwr_eSsabDbServerConnection_Up = 1,
pwr_eSsabDbServerConnection_MsgError = 2,
pwr_eSsabDbServerConnection_NoConfigFile = 3,
pwr_eSsabDbServerConnection_InitFailed = 4,
} pwr_eSsabDbServerConnection;
#ifndef pwr_cClass_Rack_SSAB
#define pwr_cClass_Rack_SSAB 4194631872UL
#endif
pwr_sClass_Rack_SSAB
typedef struct {
pwr_tUInt16 IOSysType pwr_dAlignLW;
pwr_tString80 Description pwr_dAlignW;
pwr_tUInt16 MaxNoOfCards pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Rack_SSAB;
#ifndef pwr_cClass_Ssab_SafetySwitch
#define pwr_cClass_Ssab_SafetySwitch 4194631688UL
#endif
pwr_sClass_Ssab_SafetySwitch
typedef struct {
pwr_sClass_BaseSafetySwitch Super pwr_dAlignLW;
} pwr_sClass_Ssab_SafetySwitch;
#ifndef pwr_cClass_Ssab_BaseACard
#define pwr_cClass_Ssab_BaseACard 4194631696UL
#endif
pwr_sClass_Ssab_BaseACard
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ssab_BaseACard;
#ifndef pwr_cClass_Ssab_BaseDiCard
#define pwr_cClass_Ssab_BaseDiCard 4194631704UL
#endif
pwr_sClass_Ssab_BaseDiCard
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
pwr_tCardMask1_1 ConvMask1 pwr_dAlignW;
pwr_tCardMask2_1 ConvMask2 pwr_dAlignW;
pwr_tCardMask1_1 InvMask1 pwr_dAlignW;
pwr_tCardMask2_1 InvMask2 pwr_dAlignW;
} pwr_sClass_Ssab_BaseDiCard;
#ifndef pwr_cClass_Ssab_BaseDoCard
#define pwr_cClass_Ssab_BaseDoCard 4194631712UL
#endif
pwr_sClass_Ssab_BaseDoCard
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
pwr_tCardMask1_1 InvMask1 pwr_dAlignW;
pwr_tCardMask2_1 InvMask2 pwr_dAlignW;
pwr_tCardMask1_1 TestMask1 pwr_dAlignW;
pwr_tCardMask2_1 TestMask2 pwr_dAlignW;
pwr_tCardMask1_1 TestValue1 pwr_dAlignW;
pwr_tCardMask2_1 TestValue2 pwr_dAlignW;
pwr_tCardMask1_1 FixedOutValue1 pwr_dAlignW;
pwr_tCardMask2_1 FixedOutValue2 pwr_dAlignW;
} pwr_sClass_Ssab_BaseDoCard;
#ifndef pwr_cClass_Ssab_BaseMCard
#define pwr_cClass_Ssab_BaseMCard 4194631928UL
#endif
pwr_sClass_Ssab_BaseMCard
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt16 MaxNoOfAiChannels pwr_dAlignW;
pwr_tUInt16 MaxNoOfAoChannels pwr_dAlignW;
pwr_tUInt16 MaxNoOfDiChannels pwr_dAlignW;
pwr_tUInt16 MaxNoOfDoChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
pwr_tCardMask1_1 DiConvMask pwr_dAlignW;
pwr_tCardMask1_1 DiInvMask pwr_dAlignW;
pwr_tCardMask1_1 DoInvMask pwr_dAlignW;
pwr_tCardMask1_1 DoTestMask pwr_dAlignW;
pwr_tCardMask1_1 DoTestValue pwr_dAlignW;
pwr_tCardMask1_1 DoFixedOutValue pwr_dAlignW;
} pwr_sClass_Ssab_BaseMCard;
#ifndef pwr_cClass_Ssab_AI32uP
#define pwr_cClass_Ssab_AI32uP 4194631720UL
#endif
pwr_sClass_Ssab_AI32uP
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAi Ch01 pwr_dAlignLW;
pwr_sClass_ChanAi Ch02 pwr_dAlignLW;
pwr_sClass_ChanAi Ch03 pwr_dAlignLW;
pwr_sClass_ChanAi Ch04 pwr_dAlignLW;
pwr_sClass_ChanAi Ch05 pwr_dAlignLW;
pwr_sClass_ChanAi Ch06 pwr_dAlignLW;
pwr_sClass_ChanAi Ch07 pwr_dAlignLW;
pwr_sClass_ChanAi Ch08 pwr_dAlignLW;
pwr_sClass_ChanAi Ch09 pwr_dAlignLW;
pwr_sClass_ChanAi Ch10 pwr_dAlignLW;
pwr_sClass_ChanAi Ch11 pwr_dAlignLW;
pwr_sClass_ChanAi Ch12 pwr_dAlignLW;
pwr_sClass_ChanAi Ch13 pwr_dAlignLW;
pwr_sClass_ChanAi Ch14 pwr_dAlignLW;
pwr_sClass_ChanAi Ch15 pwr_dAlignLW;
pwr_sClass_ChanAi Ch16 pwr_dAlignLW;
pwr_sClass_ChanAi Ch17 pwr_dAlignLW;
pwr_sClass_ChanAi Ch18 pwr_dAlignLW;
pwr_sClass_ChanAi Ch19 pwr_dAlignLW;
pwr_sClass_ChanAi Ch20 pwr_dAlignLW;
pwr_sClass_ChanAi Ch21 pwr_dAlignLW;
pwr_sClass_ChanAi Ch22 pwr_dAlignLW;
pwr_sClass_ChanAi Ch23 pwr_dAlignLW;
pwr_sClass_ChanAi Ch24 pwr_dAlignLW;
pwr_sClass_ChanAi Ch25 pwr_dAlignLW;
pwr_sClass_ChanAi Ch26 pwr_dAlignLW;
pwr_sClass_ChanAi Ch27 pwr_dAlignLW;
pwr_sClass_ChanAi Ch28 pwr_dAlignLW;
pwr_sClass_ChanAi Ch29 pwr_dAlignLW;
pwr_sClass_ChanAi Ch30 pwr_dAlignLW;
pwr_sClass_ChanAi Ch31 pwr_dAlignLW;
pwr_sClass_ChanAi Ch32 pwr_dAlignLW;
} pwr_sClass_Ssab_AI32uP;
#ifndef pwr_cClass_Ssab_AI16uP
#define pwr_cClass_Ssab_AI16uP 4194631768UL
#endif
pwr_sClass_Ssab_AI16uP
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAi Ch01 pwr_dAlignLW;
pwr_sClass_ChanAi Ch02 pwr_dAlignLW;
pwr_sClass_ChanAi Ch03 pwr_dAlignLW;
pwr_sClass_ChanAi Ch04 pwr_dAlignLW;
pwr_sClass_ChanAi Ch05 pwr_dAlignLW;
pwr_sClass_ChanAi Ch06 pwr_dAlignLW;
pwr_sClass_ChanAi Ch07 pwr_dAlignLW;
pwr_sClass_ChanAi Ch08 pwr_dAlignLW;
pwr_sClass_ChanAi Ch09 pwr_dAlignLW;
pwr_sClass_ChanAi Ch10 pwr_dAlignLW;
pwr_sClass_ChanAi Ch11 pwr_dAlignLW;
pwr_sClass_ChanAi Ch12 pwr_dAlignLW;
pwr_sClass_ChanAi Ch13 pwr_dAlignLW;
pwr_sClass_ChanAi Ch14 pwr_dAlignLW;
pwr_sClass_ChanAi Ch15 pwr_dAlignLW;
pwr_sClass_ChanAi Ch16 pwr_dAlignLW;
} pwr_sClass_Ssab_AI16uP;
#ifndef pwr_cClass_Ssab_AI8uP
#define pwr_cClass_Ssab_AI8uP 4194631776UL
#endif
pwr_sClass_Ssab_AI8uP
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAi Ch01 pwr_dAlignLW;
pwr_sClass_ChanAi Ch02 pwr_dAlignLW;
pwr_sClass_ChanAi Ch03 pwr_dAlignLW;
pwr_sClass_ChanAi Ch04 pwr_dAlignLW;
pwr_sClass_ChanAi Ch05 pwr_dAlignLW;
pwr_sClass_ChanAi Ch06 pwr_dAlignLW;
pwr_sClass_ChanAi Ch07 pwr_dAlignLW;
pwr_sClass_ChanAi Ch08 pwr_dAlignLW;
} pwr_sClass_Ssab_AI8uP;
#ifndef pwr_cClass_Ssab_AO8uP
#define pwr_cClass_Ssab_AO8uP 4194631728UL
#endif
pwr_sClass_Ssab_AO8uP
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAo Ch01 pwr_dAlignLW;
pwr_sClass_ChanAo Ch02 pwr_dAlignLW;
pwr_sClass_ChanAo Ch03 pwr_dAlignLW;
pwr_sClass_ChanAo Ch04 pwr_dAlignLW;
pwr_sClass_ChanAo Ch05 pwr_dAlignLW;
pwr_sClass_ChanAo Ch06 pwr_dAlignLW;
pwr_sClass_ChanAo Ch07 pwr_dAlignLW;
pwr_sClass_ChanAo Ch08 pwr_dAlignLW;
} pwr_sClass_Ssab_AO8uP;
#ifndef pwr_cClass_Ssab_AO8uPL
#define pwr_cClass_Ssab_AO8uPL 4194631792UL
#endif
pwr_sClass_Ssab_AO8uPL
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAo Ch01 pwr_dAlignLW;
pwr_sClass_ChanAo Ch02 pwr_dAlignLW;
pwr_sClass_ChanAo Ch03 pwr_dAlignLW;
pwr_sClass_ChanAo Ch04 pwr_dAlignLW;
pwr_sClass_ChanAo Ch05 pwr_dAlignLW;
pwr_sClass_ChanAo Ch06 pwr_dAlignLW;
pwr_sClass_ChanAo Ch07 pwr_dAlignLW;
pwr_sClass_ChanAo Ch08 pwr_dAlignLW;
} pwr_sClass_Ssab_AO8uPL;
#ifndef pwr_cClass_Ssab_AO16uP_Logger
#define pwr_cClass_Ssab_AO16uP_Logger 4194631800UL
#endif
pwr_sClass_Ssab_AO16uP_Logger
typedef struct {
pwr_sClass_Ssab_BaseACard Super pwr_dAlignLW;
pwr_sClass_ChanAo Ch01 pwr_dAlignLW;
pwr_sClass_ChanAo Ch02 pwr_dAlignLW;
pwr_sClass_ChanAo Ch03 pwr_dAlignLW;
pwr_sClass_ChanAo Ch04 pwr_dAlignLW;
pwr_sClass_ChanAo Ch05 pwr_dAlignLW;
pwr_sClass_ChanAo Ch06 pwr_dAlignLW;
pwr_sClass_ChanAo Ch07 pwr_dAlignLW;
pwr_sClass_ChanAo Ch08 pwr_dAlignLW;
pwr_sClass_ChanAo Ch09 pwr_dAlignLW;
pwr_sClass_ChanAo Ch10 pwr_dAlignLW;
pwr_sClass_ChanAo Ch11 pwr_dAlignLW;
pwr_sClass_ChanAo Ch12 pwr_dAlignLW;
pwr_sClass_ChanAo Ch13 pwr_dAlignLW;
pwr_sClass_ChanAo Ch14 pwr_dAlignLW;
pwr_sClass_ChanAo Ch15 pwr_dAlignLW;
pwr_sClass_ChanAo Ch16 pwr_dAlignLW;
} pwr_sClass_Ssab_AO16uP_Logger;
#ifndef pwr_cClass_Ssab_DI32D
#define pwr_cClass_Ssab_DI32D 4194631736UL
#endif
pwr_sClass_Ssab_DI32D
typedef struct {
pwr_sClass_Ssab_BaseDiCard Super pwr_dAlignLW;
pwr_sClass_ChanDi Ch01 pwr_dAlignLW;
pwr_sClass_ChanDi Ch02 pwr_dAlignLW;
pwr_sClass_ChanDi Ch03 pwr_dAlignLW;
pwr_sClass_ChanDi Ch04 pwr_dAlignLW;
pwr_sClass_ChanDi Ch05 pwr_dAlignLW;
pwr_sClass_ChanDi Ch06 pwr_dAlignLW;
pwr_sClass_ChanDi Ch07 pwr_dAlignLW;
pwr_sClass_ChanDi Ch08 pwr_dAlignLW;
pwr_sClass_ChanDi Ch09 pwr_dAlignLW;
pwr_sClass_ChanDi Ch10 pwr_dAlignLW;
pwr_sClass_ChanDi Ch11 pwr_dAlignLW;
pwr_sClass_ChanDi Ch12 pwr_dAlignLW;
pwr_sClass_ChanDi Ch13 pwr_dAlignLW;
pwr_sClass_ChanDi Ch14 pwr_dAlignLW;
pwr_sClass_ChanDi Ch15 pwr_dAlignLW;
pwr_sClass_ChanDi Ch16 pwr_dAlignLW;
pwr_sClass_ChanDi Ch17 pwr_dAlignLW;
pwr_sClass_ChanDi Ch18 pwr_dAlignLW;
pwr_sClass_ChanDi Ch19 pwr_dAlignLW;
pwr_sClass_ChanDi Ch20 pwr_dAlignLW;
pwr_sClass_ChanDi Ch21 pwr_dAlignLW;
pwr_sClass_ChanDi Ch22 pwr_dAlignLW;
pwr_sClass_ChanDi Ch23 pwr_dAlignLW;
pwr_sClass_ChanDi Ch24 pwr_dAlignLW;
pwr_sClass_ChanDi Ch25 pwr_dAlignLW;
pwr_sClass_ChanDi Ch26 pwr_dAlignLW;
pwr_sClass_ChanDi Ch27 pwr_dAlignLW;
pwr_sClass_ChanDi Ch28 pwr_dAlignLW;
pwr_sClass_ChanDi Ch29 pwr_dAlignLW;
pwr_sClass_ChanDi Ch30 pwr_dAlignLW;
pwr_sClass_ChanDi Ch31 pwr_dAlignLW;
pwr_sClass_ChanDi Ch32 pwr_dAlignLW;
} pwr_sClass_Ssab_DI32D;
#ifndef pwr_cClass_Ssab_DO32DKS
#define pwr_cClass_Ssab_DO32DKS 4194631744UL
#endif
pwr_sClass_Ssab_DO32DKS
typedef struct {
pwr_sClass_Ssab_BaseDoCard Super pwr_dAlignLW;
pwr_sClass_ChanDo Ch01 pwr_dAlignLW;
pwr_sClass_ChanDo Ch02 pwr_dAlignLW;
pwr_sClass_ChanDo Ch03 pwr_dAlignLW;
pwr_sClass_ChanDo Ch04 pwr_dAlignLW;
pwr_sClass_ChanDo Ch05 pwr_dAlignLW;
pwr_sClass_ChanDo Ch06 pwr_dAlignLW;
pwr_sClass_ChanDo Ch07 pwr_dAlignLW;
pwr_sClass_ChanDo Ch08 pwr_dAlignLW;
pwr_sClass_ChanDo Ch09 pwr_dAlignLW;
pwr_sClass_ChanDo Ch10 pwr_dAlignLW;
pwr_sClass_ChanDo Ch11 pwr_dAlignLW;
pwr_sClass_ChanDo Ch12 pwr_dAlignLW;
pwr_sClass_ChanDo Ch13 pwr_dAlignLW;
pwr_sClass_ChanDo Ch14 pwr_dAlignLW;
pwr_sClass_ChanDo Ch15 pwr_dAlignLW;
pwr_sClass_ChanDo Ch16 pwr_dAlignLW;
pwr_sClass_ChanDo Ch17 pwr_dAlignLW;
pwr_sClass_ChanDo Ch18 pwr_dAlignLW;
pwr_sClass_ChanDo Ch19 pwr_dAlignLW;
pwr_sClass_ChanDo Ch20 pwr_dAlignLW;
pwr_sClass_ChanDo Ch21 pwr_dAlignLW;
pwr_sClass_ChanDo Ch22 pwr_dAlignLW;
pwr_sClass_ChanDo Ch23 pwr_dAlignLW;
pwr_sClass_ChanDo Ch24 pwr_dAlignLW;
pwr_sClass_ChanDo Ch25 pwr_dAlignLW;
pwr_sClass_ChanDo Ch26 pwr_dAlignLW;
pwr_sClass_ChanDo Ch27 pwr_dAlignLW;
pwr_sClass_ChanDo Ch28 pwr_dAlignLW;
pwr_sClass_ChanDo Ch29 pwr_dAlignLW;
pwr_sClass_ChanDo Ch30 pwr_dAlignLW;
pwr_sClass_ChanDo Ch31 pwr_dAlignLW;
pwr_sClass_ChanDo Ch32 pwr_dAlignLW;
} pwr_sClass_Ssab_DO32DKS;
#ifndef pwr_cClass_Ssab_DO32DKS_Stall
#define pwr_cClass_Ssab_DO32DKS_Stall 4194631784UL
#endif
pwr_sClass_Ssab_DO32DKS_Stall
typedef struct {
pwr_sClass_Ssab_BaseDoCard Super pwr_dAlignLW;
pwr_sClass_ChanDo Ch01 pwr_dAlignLW;
pwr_sClass_ChanDo Ch02 pwr_dAlignLW;
pwr_sClass_ChanDo Ch03 pwr_dAlignLW;
pwr_sClass_ChanDo Ch04 pwr_dAlignLW;
pwr_sClass_ChanDo Ch05 pwr_dAlignLW;
pwr_sClass_ChanDo Ch06 pwr_dAlignLW;
pwr_sClass_ChanDo Ch07 pwr_dAlignLW;
pwr_sClass_ChanDo Ch08 pwr_dAlignLW;
pwr_sClass_ChanDo Ch09 pwr_dAlignLW;
pwr_sClass_ChanDo Ch10 pwr_dAlignLW;
pwr_sClass_ChanDo Ch11 pwr_dAlignLW;
pwr_sClass_ChanDo Ch12 pwr_dAlignLW;
pwr_sClass_ChanDo Ch13 pwr_dAlignLW;
pwr_sClass_ChanDo Ch14 pwr_dAlignLW;
pwr_sClass_ChanDo Ch15 pwr_dAlignLW;
pwr_sClass_ChanDo Ch16 pwr_dAlignLW;
pwr_sClass_ChanDo Ch17 pwr_dAlignLW;
pwr_sClass_ChanDo Ch18 pwr_dAlignLW;
pwr_sClass_ChanDo Ch19 pwr_dAlignLW;
pwr_sClass_ChanDo Ch20 pwr_dAlignLW;
pwr_sClass_ChanDo Ch21 pwr_dAlignLW;
pwr_sClass_ChanDo Ch22 pwr_dAlignLW;
pwr_sClass_ChanDo Ch23 pwr_dAlignLW;
pwr_sClass_ChanDo Ch24 pwr_dAlignLW;
pwr_sClass_ChanDo Ch25 pwr_dAlignLW;
pwr_sClass_ChanDo Ch26 pwr_dAlignLW;
pwr_sClass_ChanDo Ch27 pwr_dAlignLW;
pwr_sClass_ChanDo Ch28 pwr_dAlignLW;
pwr_sClass_ChanDo Ch29 pwr_dAlignLW;
pwr_sClass_ChanDo Ch30 pwr_dAlignLW;
pwr_sClass_ChanDo Ch31 pwr_dAlignLW;
pwr_sClass_ChanDo Ch32 pwr_dAlignLW;
} pwr_sClass_Ssab_DO32DKS_Stall;
#ifndef pwr_cClass_Ssab_CO4uP
#define pwr_cClass_Ssab_CO4uP 4194631752UL
#endif
pwr_sClass_Ssab_CO4uP
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tMask ConvMask pwr_dAlignW;
pwr_tUInt16 MaxNoOfCounters pwr_dAlignW;
pwr_tBoolean COAbsFlag[4] pwr_dAlignW;
pwr_tSsabCoNoOfBitsEnum NoOfBits[4] pwr_dAlignW;
pwr_tBoolean COWrFlag[4] pwr_dAlignW;
pwr_tSsabCoMulCountEnum MulCount[4] pwr_dAlignW;
pwr_tSsabCoDivCountEnum DivCount[4] pwr_dAlignW;
pwr_tBoolean CopWrRough[4] pwr_dAlignW;
pwr_tBoolean CopWrFine[4] pwr_dAlignW;
pwr_tBoolean LoadWrReg[4] pwr_dAlignW;
pwr_tBoolean LengthMeasurement[4] pwr_dAlignW;
pwr_tBoolean SpeedMeasurement[4] pwr_dAlignW;
pwr_tUInt32 SyncRawValue[4] pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
pwr_sClass_ChanCo Ch1 pwr_dAlignLW;
pwr_sClass_ChanCo Ch2 pwr_dAlignLW;
pwr_sClass_ChanCo Ch3 pwr_dAlignLW;
pwr_sClass_ChanCo Ch4 pwr_dAlignLW;
} pwr_sClass_Ssab_CO4uP;
#ifndef pwr_cClass_Ssab_PIDuP
#define pwr_cClass_Ssab_PIDuP 4194631920UL
#endif
pwr_sClass_Ssab_PIDuP
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tObjid PidXCon pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ssab_PIDuP;
#ifndef pwr_cClass_Ssab_MIO3102uP
#define pwr_cClass_Ssab_MIO3102uP 4194631936UL
#endif
pwr_sClass_Ssab_MIO3102uP
typedef struct {
pwr_sClass_Ssab_BaseMCard Super pwr_dAlignLW;
pwr_sClass_ChanAi ChAi01 pwr_dAlignLW;
pwr_sClass_ChanAi ChAi02 pwr_dAlignLW;
pwr_sClass_ChanAi ChAi03 pwr_dAlignLW;
pwr_sClass_ChanAo ChAo01 pwr_dAlignLW;
pwr_sClass_ChanDo ChDo01 pwr_dAlignLW;
pwr_sClass_ChanDo ChDo02 pwr_dAlignLW;
} pwr_sClass_Ssab_MIO3102uP;
#ifndef pwr_cClass_Ai_AI32uP
#define pwr_cClass_Ai_AI32uP 4194631808UL
#endif
pwr_sClass_Ai_AI32uP
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ai_AI32uP;
pwr_sdClass_Ai_AI32uP
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Ai_AI32uP;
#ifndef pwr_cClass_Ai_HVAI32
#define pwr_cClass_Ai_HVAI32 4194631816UL
#endif
pwr_sClass_Ai_HVAI32
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tFloat32 DevPolyCoef0 pwr_dAlignW;
pwr_tFloat32 DevPolyCoef1 pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ai_HVAI32;
pwr_sdClass_Ai_HVAI32
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Ai_HVAI32;
#ifndef pwr_cClass_Ao_AO8uP
#define pwr_cClass_Ao_AO8uP 4194631824UL
#endif
pwr_sClass_Ao_AO8uP
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tFloat32 DevPolyCoef0 pwr_dAlignW;
pwr_tFloat32 DevPolyCoef1 pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ao_AO8uP;
pwr_sdClass_Ao_AO8uP
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Ao_AO8uP;
#ifndef pwr_cClass_Ao_HVAO4
#define pwr_cClass_Ao_HVAO4 4194631832UL
#endif
pwr_sClass_Ao_HVAO4
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tFloat32 DevPolyCoef0 pwr_dAlignW;
pwr_tFloat32 DevPolyCoef1 pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Ao_HVAO4;
pwr_sdClass_Ao_HVAO4
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Ao_HVAO4;
#ifndef pwr_cClass_Co_CO4uP
#define pwr_cClass_Co_CO4uP 4194631840UL
#endif
pwr_sClass_Co_CO4uP
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tMask ConvMask pwr_dAlignW;
pwr_tUInt16 MaxNoOfCounters pwr_dAlignW;
pwr_tBoolean COAbsFlag[4] pwr_dAlignW;
pwr_tSsabCoNoOfBitsEnum NoOfBits[4] pwr_dAlignW;
pwr_tBoolean COWrFlag[4] pwr_dAlignW;
pwr_tSsabCoMulCountEnum MulCount[4] pwr_dAlignW;
pwr_tSsabCoDivCountEnum DivCount[4] pwr_dAlignW;
pwr_tBoolean CopWrRough[4] pwr_dAlignW;
pwr_tBoolean CopWrFine[4] pwr_dAlignW;
pwr_tBoolean LoadWrReg[4] pwr_dAlignW;
pwr_tBoolean LengthMeasurement[4] pwr_dAlignW;
pwr_tBoolean SpeedMeasurement[4] pwr_dAlignW;
pwr_tUInt32 SyncRawValue[4] pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Co_CO4uP;
pwr_sdClass_Co_CO4uP
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Co_CO4uP;
#ifndef pwr_cClass_Co_PI24BO
#define pwr_cClass_Co_PI24BO 4194631848UL
#endif
pwr_sClass_Co_PI24BO
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tMask ConvMask pwr_dAlignW;
pwr_tUInt16 MaxNoOfCounters pwr_dAlignW;
pwr_tBoolean COAbsFlag[4] pwr_dAlignW;
pwr_tSsabCoNoOfBitsEnum NoOfBits[4] pwr_dAlignW;
pwr_tBoolean COWrFlag[4] pwr_dAlignW;
pwr_tSsabCoMulCountEnum MulCount[4] pwr_dAlignW;
pwr_tSsabCoDivCountEnum DivCount[4] pwr_dAlignW;
pwr_tBoolean CopWrRough[4] pwr_dAlignW;
pwr_tBoolean CopWrFine[4] pwr_dAlignW;
pwr_tBoolean LoadWrReg[4] pwr_dAlignW;
pwr_tBoolean LengthMeasurement[4] pwr_dAlignW;
pwr_tBoolean SpeedMeasurement[4] pwr_dAlignW;
pwr_tUInt32 SyncRawValue[4] pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Co_PI24BO;
pwr_sdClass_Co_PI24BO
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Co_PI24BO;
#ifndef pwr_cClass_Di_DIX2
#define pwr_cClass_Di_DIX2 4194631856UL
#endif
pwr_sClass_Di_DIX2
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tMask ConvMask1 pwr_dAlignW;
pwr_tMask ConvMask2 pwr_dAlignW;
pwr_tMask InvMask1 pwr_dAlignW;
pwr_tMask InvMask2 pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Di_DIX2;
pwr_sdClass_Di_DIX2
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Di_DIX2;
#ifndef pwr_cClass_Do_HVDO32
#define pwr_cClass_Do_HVDO32 4194631864UL
#endif
pwr_sClass_Do_HVDO32
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString40 DevName pwr_dAlignW;
pwr_tUInt32 ErrorCount pwr_dAlignW;
pwr_tUInt32 ErrorSoftLimit pwr_dAlignW;
pwr_tUInt32 ErrorHardLimit pwr_dAlignW;
pwr_tMask InvMask1 pwr_dAlignW;
pwr_tMask InvMask2 pwr_dAlignW;
pwr_tMask TestMask1 pwr_dAlignW;
pwr_tMask TestMask2 pwr_dAlignW;
pwr_tUInt16 TestValue1 pwr_dAlignW;
pwr_tUInt16 TestValue2 pwr_dAlignW;
pwr_tUInt16 FixedOutValue1 pwr_dAlignW;
pwr_tUInt16 FixedOutValue2 pwr_dAlignW;
pwr_tUInt16 MaxNoOfChannels pwr_dAlignW;
pwr_tUInt32 RegAddress pwr_dAlignW;
pwr_tUInt32 SwitchSettings pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tURL DataSheet pwr_dAlignW;
} pwr_sClass_Do_HVDO32;
pwr_sdClass_Do_HVDO32
typedef struct {
pwr_tUInt32 ChannelAllocation pwr_dAlignLW;
} pwr_sdClass_Do_HVDO32;
#ifndef pwr_cClass_PidX
#define pwr_cClass_PidX 4194631888UL
#endif
pwr_sClass_PidX
typedef struct {
pwr_tFloat32 *SetValP pwr_dAlignLW;
pwr_tFloat32 SetVal pwr_dAlignLW;
pwr_tFloat32 *BiasDP pwr_dAlignLW;
pwr_tFloat32 BiasD pwr_dAlignLW;
pwr_tFloat32 *ForcValP pwr_dAlignLW;
pwr_tFloat32 ForcVal pwr_dAlignLW;
pwr_tBoolean *ForceP pwr_dAlignLW;
pwr_tBoolean Force pwr_dAlignLW;
pwr_tBoolean *IntOffP pwr_dAlignLW;
pwr_tBoolean IntOff pwr_dAlignLW;
pwr_tString80 Description pwr_dAlignW;
pwr_tObjid Pid1uPCon pwr_dAlignW;
pwr_tFloat32 Acc pwr_dAlignW;
pwr_tFloat32 OutVal pwr_dAlignW;
pwr_tFloat32 ControlDiff pwr_dAlignW;
pwr_tFloat32 XScanTime pwr_dAlignW;
pwr_tBoolean EndMax pwr_dAlignW;
pwr_tBoolean EndMin pwr_dAlignW;
pwr_tBoolean Init pwr_dAlignW;
pwr_tPidAlgEnum PidAlg pwr_dAlignW;
pwr_tBoolean Inverse pwr_dAlignW;
pwr_tFloat32 PidGain pwr_dAlignW;
pwr_tFloat32 IntTime pwr_dAlignW;
pwr_tFloat32 DerTime pwr_dAlignW;
pwr_tFloat32 DerGain pwr_dAlignW;
pwr_tFloat32 MinOut pwr_dAlignW;
pwr_tFloat32 MaxOut pwr_dAlignW;
pwr_tFloat32 EndHys pwr_dAlignW;
pwr_tFloat32 BiasGain pwr_dAlignW;
pwr_tBoolean UseDynBias pwr_dAlignW;
pwr_tFloat32 ProcMax pwr_dAlignW;
pwr_tFloat32 ProcMin pwr_dAlignW;
pwr_tString16 ProcValueUnit pwr_dAlignW;
pwr_tFloat32 ProcFiltTime pwr_dAlignW;
pwr_tInt32 ProcRawMax pwr_dAlignW;
pwr_tInt32 ProcRawMin pwr_dAlignW;
pwr_tFloat32 BiasMax pwr_dAlignW;
pwr_tFloat32 BiasMin pwr_dAlignW;
pwr_tString16 BiasValueUnit pwr_dAlignW;
pwr_tFloat32 BiasFiltTime pwr_dAlignW;
pwr_tInt32 BiasRawMax pwr_dAlignW;
pwr_tInt32 BiasRawMin pwr_dAlignW;
pwr_tBoolean UseAo pwr_dAlignW;
pwr_tFloat32 AoMax pwr_dAlignW;
pwr_tFloat32 AoMin pwr_dAlignW;
pwr_tString16 AoValueUnit pwr_dAlignW;
pwr_tInt32 AoRawMax pwr_dAlignW;
pwr_tInt32 AoRawMin pwr_dAlignW;
pwr_tBoolean UsePos3p pwr_dAlignW;
pwr_tFloat32 PosMax pwr_dAlignW;
pwr_tFloat32 PosMin pwr_dAlignW;
pwr_tString16 PosValueUnit pwr_dAlignW;
pwr_tFloat32 PosFiltTime pwr_dAlignW;
pwr_tInt32 PosRawMax pwr_dAlignW;
pwr_tInt32 PosRawMin pwr_dAlignW;
pwr_tFloat32 ErrSta pwr_dAlignW;
pwr_tFloat32 ErrSto pwr_dAlignW;
pwr_tFloat32 Pos3pGain pwr_dAlignW;
pwr_tBoolean UseInc3p pwr_dAlignW;
pwr_tFloat32 Inc3pGain pwr_dAlignW;
pwr_tFloat32 MinTim pwr_dAlignW;
pwr_tFloat32 MaxTim pwr_dAlignW;
pwr_tFloat32 MaxInteg pwr_dAlignW;
pwr_tFloat32 PosVal pwr_dAlignW;
pwr_tFloat32 ProcVal pwr_dAlignW;
pwr_tFloat32 Bias pwr_dAlignW;
} pwr_sClass_PidX;
pwr_sdClass_PidX
typedef struct {
pwr_sPlcNode PlcNode pwr_dAlignLW;
} pwr_sdClass_PidX;
#ifndef pwr_cClass_Ssab_AntiSway
#define pwr_cClass_Ssab_AntiSway 4194631896UL
#endif
pwr_sClass_Ssab_AntiSway
typedef struct {
pwr_tVoid **otherP pwr_dAlignLW;
pwr_tVoid *other pwr_dAlignLW;
pwr_tInt32 *modeP pwr_dAlignLW;
pwr_tInt32 mode pwr_dAlignLW;
pwr_tBoolean *manualP pwr_dAlignLW;
pwr_tBoolean manual pwr_dAlignLW;
pwr_tFloat32 *uCommandP pwr_dAlignLW;
pwr_tFloat32 uCommand pwr_dAlignLW;
pwr_tFloat32 *xCommandP pwr_dAlignLW;
pwr_tFloat32 xCommand pwr_dAlignLW;
pwr_tFloat32 *xcP pwr_dAlignLW;
pwr_tFloat32 xc pwr_dAlignLW;
pwr_tFloat32 *DLcP pwr_dAlignLW;
pwr_tFloat32 DLc pwr_dAlignLW;
pwr_tFloat32 *LcP pwr_dAlignLW;
pwr_tFloat32 Lc pwr_dAlignLW;
pwr_tBoolean *umax2P pwr_dAlignLW;
pwr_tBoolean umax2 pwr_dAlignLW;
pwr_tBoolean *enableP pwr_dAlignLW;
pwr_tBoolean enable pwr_dAlignLW;
pwr_tFloat32 amax[4] pwr_dAlignW;
pwr_tFloat32 umax[5] pwr_dAlignW;
pwr_tFloat32 limits[10] pwr_dAlignW;
pwr_tInt32 compensate pwr_dAlignW;
pwr_tInt32 verbose pwr_dAlignW;
pwr_tBoolean zeroTheta pwr_dAlignW;
pwr_tMask errstatus pwr_dAlignW;
pwr_tMask autostatus pwr_dAlignW;
pwr_tBoolean reset pwr_dAlignW;
pwr_tBoolean flags[32] pwr_dAlignW;
pwr_tFloat64 aR pwr_dAlignLW;
pwr_tFloat64 uR pwr_dAlignLW;
pwr_tFloat64 xR[2] pwr_dAlignLW;
pwr_tFloat64 thR[2] pwr_dAlignLW;
pwr_tString32 Set pwr_dAlignW;
pwr_tUInt64 messageQ[2] pwr_dAlignLW;
pwr_tString80 message[2] pwr_dAlignLW;
pwr_tInt32 mparams[4] pwr_dAlignW;
pwr_tFloat32 aRO pwr_dAlignW;
pwr_tFloat32 uRO pwr_dAlignW;
pwr_tFloat32 xRO pwr_dAlignW;
pwr_tFloat32 thRO pwr_dAlignW;
pwr_tBoolean done pwr_dAlignW;
pwr_tBoolean Alarm1 pwr_dAlignW;
pwr_tBoolean Alarm2 pwr_dAlignW;
} pwr_sClass_Ssab_AntiSway;
pwr_sdClass_Ssab_AntiSway
typedef struct {
pwr_sPlcNode PlcNode pwr_dAlignLW;
} pwr_sdClass_Ssab_AntiSway;
#ifndef pwr_cClass_Ssab_ServoReg
#define pwr_cClass_Ssab_ServoReg 4194631904UL
#endif
pwr_sClass_Ssab_ServoReg
typedef struct {
pwr_tFloat32 *aRP pwr_dAlignLW;
pwr_tFloat32 aR pwr_dAlignLW;
pwr_tFloat32 *uRP pwr_dAlignLW;
pwr_tFloat32 uR pwr_dAlignLW;
pwr_tFloat32 *xRP pwr_dAlignLW;
pwr_tFloat32 xR pwr_dAlignLW;
pwr_tFloat32 *acP pwr_dAlignLW;
pwr_tFloat32 ac pwr_dAlignLW;
pwr_tFloat32 *ucP pwr_dAlignLW;
pwr_tFloat32 uc pwr_dAlignLW;
pwr_tFloat32 *xcP pwr_dAlignLW;
pwr_tFloat32 xc pwr_dAlignLW;
pwr_tFloat32 *xCommandP pwr_dAlignLW;
pwr_tFloat32 xCommand pwr_dAlignLW;
pwr_tFloat32 *umaxPP pwr_dAlignLW;
pwr_tFloat32 umaxP pwr_dAlignLW;
pwr_tFloat32 *umaxNP pwr_dAlignLW;
pwr_tFloat32 umaxN pwr_dAlignLW;
pwr_tBoolean *positioningP pwr_dAlignLW;
pwr_tBoolean positioning pwr_dAlignLW;
pwr_tBoolean *enableP pwr_dAlignLW;
pwr_tBoolean enable pwr_dAlignLW;
pwr_tFloat32 amaxS pwr_dAlignW;
pwr_tBoolean enablePID pwr_dAlignW;
pwr_tFloat32 kPID[3] pwr_dAlignW;
pwr_tFloat32 DelayPID pwr_dAlignW;
pwr_tInt32 maxdelaysteps pwr_dAlignW;
pwr_tFloat32 *RefListp pwr_dAlignLW;
pwr_tBoolean enableRamp pwr_dAlignLW;
pwr_tFloat32 DelayRamp pwr_dAlignW;
pwr_tBoolean enableDZ pwr_dAlignW;
pwr_tFloat32 DeadZone pwr_dAlignW;
pwr_tBoolean enableTDZ pwr_dAlignW;
pwr_tFloat32 TimerDeadZone pwr_dAlignW;
pwr_tFloat32 TDZTime pwr_dAlignW;
pwr_tFloat32 TDZElapsedTime pwr_dAlignW;
pwr_tFloat32 *ScanTime pwr_dAlignLW;
pwr_tFloat32 uReg pwr_dAlignLW;
pwr_tBoolean RampActive pwr_dAlignW;
pwr_tBoolean DZActive pwr_dAlignW;
pwr_tBoolean TDZActive pwr_dAlignW;
} pwr_sClass_Ssab_ServoReg;
pwr_sdClass_Ssab_ServoReg
typedef struct {
pwr_sPlcNode PlcNode pwr_dAlignLW;
} pwr_sdClass_Ssab_ServoReg;
#ifndef pwr_cClass_Ssab_RemoteRack
#define pwr_cClass_Ssab_RemoteRack 4194631912UL
#endif
pwr_sClass_Ssab_RemoteRack
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tString80 Address pwr_dAlignW;
pwr_tUInt16 LocalPort pwr_dAlignW;
pwr_tUInt16 RemotePort pwr_dAlignW;
pwr_tIoProcessMask Process pwr_dAlignW;
pwr_tObjid ThreadObject pwr_dAlignW;
pwr_tSsabStallActionEnum StallAction pwr_dAlignW;
pwr_tStatus Status pwr_dAlignW;
pwr_tUInt32 RX_packets pwr_dAlignW;
pwr_tUInt32 TX_packets pwr_dAlignW;
} pwr_sClass_Ssab_RemoteRack;
#ifndef pwr_cClass_Ssab_ExportRtdbServer
#define pwr_cClass_Ssab_ExportRtdbServer 4194631944UL
#endif
pwr_sClass_Ssab_ExportRtdbServer
typedef struct {
pwr_tString80 Description pwr_dAlignLW;
pwr_tFloat32 ScanTime pwr_dAlignW;
pwr_tString80 Topic pwr_dAlignW;
pwr_tString80 KafkaConfigFile pwr_dAlignW;
pwr_tURL SchemaRegistryURL pwr_dAlignW;
pwr_tSsabDbServerConnection ServerConnection pwr_dAlignW;
pwr_tUInt32 SendCnt pwr_dAlignW;
} pwr_sClass_Ssab_ExportRtdbServer;
#endif